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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. march 2007 rev 1 1/20 20 L6562A transition-mode pfc controller features proprietary multiplier design for minimum thd very accurate adjustable output overvoltage protection ultra-low (30 a) start-up current low ( 2.5 ma) quiescent current digital leading-edge blanking on current sense disable function on e/a input 1.4% (@ t j = 25 c) internal reference voltage -600/+800ma totem pole gate driver with active pull-down during uvlo and voltage clamp dip-8/so-8 packages applications pfc pre-regulators for: iec61000-3-2 compliant smps (flat tv, desktop pc, games) hi-end ac-dc adapter/charger up to 400w electronic ballast entry level server & web server so-8 dip-8 www.st.com figure 1. block diagram
contents L6562A 2/20 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3 thd optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.4 operating with no auxiliary winding on the boost inductor . . . . . . . . . . . . 12 6.5 comparison between the L6562A and the l6562 . . . . . . . . . . . . . . . . . . 13 7 application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
L6562A description 3/20 1 description the L6562A is a current-mode pfc controller operating in transition mode (tm). coming with the same pin-out as its predecessors l6561 and l6562, it offers improved performance. the highly linear multiplier includes a specia l circuit, able to reduce ac input current distortion, that allows wide-range-mains operation with an extremely low thd, even over a large load range. the output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1.4% @t j = 25c) internal voltage reference. the device features extremely low consumption (60a max. before start-up and <5 ma operating) and includes a disable function suitable for ic remote on/off, which makes it easier to comply with energy saving requirements (blue angel, energystar, energy2000, etc.). an effective two-step ovp enables to safely handle overvoltages either occurring at start-up or resulting from load disconnection. the totem-pole output stage, capable of 600 ma source and 800 ma sink current, is suitable to drive high current mosfets or igbts. this, combined with the other features and the possibility to operate with the proprietary fixed-off-time co ntrol, makes the device an excellent low-cost solution for en61000-3-2 compliant smps in excess of 350w.
pin settings L6562A 4/20 2 pin settings 2.1 pin connection figure 2. pin connection (top view) 2.2 pin description zcd inv comp mult cs vcc gd gnd 1 2 3 4 8 7 6 5 table 1. pin description pin n name description 1inv inverting input of the error amplifier. the information on the output voltage of the pfc pre-regulator is fed into this pin through a resistor divider. the pin doubles as an on/off control input. 2comp output of the error amplifier. a com pensation network is placed between this pin and inv to achieve stability of the voltage control loop and ensure high power factor and low thd. 3mult main input to the multiplier. this pin is connected to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. 4cs input to the pwm comparator. the curre nt flowing in the mosfet is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped reference, generated by the multiplier, to determine mosfet?s turn-off. the pin is equipped with 200 ns leading-edge blanking for improved noise immunity. 5zcd boost inductor?s demagnetization sensing input for transition-mode operation. a negative-going edge triggers mosfet?s turn-on. 6 gnd ground. current return for both the sig nal part of the ic and the gate driver. 7gd gate driver output. the totem pole output stage is able to drive power mosfet?s and igbt?s with a peak curr ent of 600 ma source and 800 ma sink. the high-level voltage of this pi n is clamped at about 12v to avoid excessive gate voltages in case the pin is supplied with a high vcc. 8vcc supply voltage of both the signal part of the ic and the gate driver. the supply voltage upper limit is extended to 22v min. to provide more headroom for supply voltage changes.
L6562A maximum ratings 5/20 3 maximum ratings 4 thermal data table 2. absolute maximum ratings symbol pin parameter value unit v cc 8 ic supply voltage (i cc 20ma) self-limited v i gd 7 output totem pole peak current self-limited a --- 1 to 4 analog inputs & outputs -0.3 to 8 v i zcd 5 zero current detecto r max. current 10 ma table 3. thermal data symbol parameter value unit so8 dip8 r thja max. thermal resistance, junction-to- ambient 150 100 c/w p tot power dissipation @t a = 50c 0.65 1 w t j junction temperature operating range -40 to 150 c t stg storage temperature -55 to 150 c
electrical characteristics L6562A 6/20 5 electrical characteristics table 4. electrical characteristics ( -25c < t j < +125c, v cc = 12v, c o = 1nf; unless otherwise specified) symbol parameter test condition min typ max unit supply voltage v cc operating range after turn-on 10.5 22 v vcc on turn-on threshold 11.5 12.5 13.5 v vcc off turn-off threshold (1) 9.5 10 10.5 v hys hysteresis 2.2 2.8 v v z zener voltage i cc = 20ma 22 25 28 v supply current i start-up start-up current before turn-on, v cc = 11v 30 60 a i q quiescent current after turn-on 2.5 3.75 ma i cc operating supply current @ 70khz 3.5 5 ma i q quiescent current during ovp (either static or dynamic) or v inv 150mv 1.7 2.2 ma multiplier input i mult input bias current v mult = 0 to 4v -1 a v mult linear operation range 0 to 3 v output max. slope v mult = 0 to 1v, v comp = upper clamp 11.1 v/v k gain (2) v mult = 1v, v comp = 4v, 0.32 0.38 0.44 v error amplifier v inv voltage feedback input threshold t j = 25 c 2.465 2.5 2.535 v 10.5v < v cc < 22v (1) 2.44 2.56 line regulation v cc = 10.5v to 22v 25mv i inv input bias current v inv = 0 to 3v -1 a gv voltage gain open loop 60 80 db gb gain-bandwidth product 1 mhz i comp source current v comp = 4v, v inv = 2.4v -2 -3.5 -5 ma sink current v comp = 4v, v inv = 2.6v 2.5 4.5 ma v cs ? v mult ? ---------------------
L6562A electrical characteristics 7/20 symbol parameter test condition min typ max unit v comp upper clamp voltage i source = 0.5ma 5.3 5.7 6 v lower clamp voltage i sink = 0.5ma (1) 2.12.252.4 v v invdis disable threshold 150 200 250 mv v inven restart threshold 450 520 mv output overvoltage i ovp dynamic ovp triggering current 23.5 27 30.5 a hys hysteresis (3) 20 a static ovp threshold (1) 2.12.252.4 v current sense comparator i cs input bias current v cs = 0 -1 a t leb leading edge blanking 100 200 300 ns td (h-l) delay to output 175 ns v cs current sense clamp v comp = upper clamp 1.0 1.08 1.16 v vcs offset current sense offset v mult = 0 25 mv v mult = 2.5v 5 zero current detector v zcdh upper clamp voltage i zcd = 2.5ma 5.0 5.7 6.5 v v zcdl lower clamp voltage i zcd = - 2.5ma -0.3 0 0.3 v v zcda arming voltage (positive-going edge) (3) 1.4 v v zcdt triggering voltage (negative-going edge) (3) 0.7 v i zcdb input bias current v zcd = 1 to 4.5v 2a i zcdsrc source current capability -2.5 ma i zcdsnk sink current capability 2.5 ma starter t start start timer period 75 190 300 s table 4. electrical characteristics (continued) ( -25c < t j < +125c, v cc = 12v, c o = 1nf; unless otherwise specified)
electrical characteristics L6562A 8/20 symbol parameter test condition min typ max unit gate driver v ol output low voltage i sink = 100ma 1.0 v v oh output high voltage i source = 5ma 9.8 10.3 v i srcpk peak source current -0.6 a i snkpk peak sink current 0.8 a t f voltage fall time 30 ns t r voltage rise time 85 ns v oclamp output clamp voltage i source = 5ma; vcc = 20 v 10 12 15 v uvlo saturation vcc = 0 to v ccon , i sink = 2 ma 1.1 v 1. all the parameters are in tracking 2. the multiplier output is given by: 3. parameters guaranteed by design, functionality tested in production. table 4. electrical characteristics (continued) ( -25c < t j < +125c, v cc = 12v, c o = 1nf; unless otherwise specified) ( ) 5 . 2 v v k v comp mult cs ? ? = ?
L6562A application information 9/20 6 application information 6.1 overvoltage protection under steady-state conditions, the voltage control loop keeps the output voltage vo of a pfc pre-regulator close to its nominal value, se t by the resistors r1 and r2 of the output divider. neglecting ripple components, the current through r1, i r1 , equals that through r2, i r2 . considering that the non-inverting input of th e error amplifier is inte rnally referenced at 2.5v, also the voltage at pin inv will be 2.5v, then: equation 1 if the output voltage experiences an abrupt change ? vo > 0 due to a load drop, the voltage at pin inv will be kept at 2.5v by the loca l feedback of the error amplifier, a network connected between pins inv and comp that in troduces a long time constant to achieve high pf (this is why ? vo can be large). as a result, the current through r2 will remain equal to 2.5/r2 but that th rough r1 will become: equation 2 the difference current ? i r1 =i' r1 -i r2 =i' r1 -i r1 = ? vo/r1 will flow through the compensation network and enter the error amplifier output (p in comp). this curren t is monitored inside the device and if it reaches about 24a the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy delivered to the ou tput. as the current exceeds 27a, the ovp is triggered (dynamic ov p): the gate-drive is forced low to switch off the external power transistor and the ic put in an idle state. this co ndition is maintained until the current falls below approximately 7a, which re-enables the internal starter and allows switching to restart. the output ? vo that is able to trigger the dynamic ovp function is then: equation 3 ? v o = r1 20 10 - 6 an important advantage of this technique is that the ov level can be set independently of the regulated output voltage: the latter depends on the ratio of r1 to r2, the former on the individual value of r1. another advantage is the precision: the tolerance of the detection current is 13%, i.e. 13% tolerance on ? vo. since ? vo << vo, the tolerance on the absolute value will be prop ortionally reduced. i r2 i r1 2.5 r2 ------- - v o 2.5 ? r1 --------------------- - === i ' r1 v o 2.5 ? v o ? + r1 --------------------------------------- - =
application information L6562A 10/20 example: vo = 400v, ? vo = 40v. then: r1 = 40v/27a 1.5m ? ; r2 = 1.5 m ? 2.5/(400-2.5) = 9.43k ? . the tolerance on the ovp level due to the L6562A will be 400.13 = 5.3v, that is 1.2%. when the load of a pfc pre-regulator is very low, the output voltage tends to stay steadily above the nominal value, which cannot be handled by the dynamic ovp. if this occurs, however, the error amplifier ou tput will saturate low; hence, when this is detected the external power transistor is switched off and the ic put in an idle state (static ovp). normal operation is resumed as the error amplifier goes back into its linear region. as a result, the device will work in burst-mode, with a repetition rate that can be very low. when either ovp is activated the quiescent co nsumption of the ic is reduced to minimize the discharge of the vcc capacitor and increa se the hold-up capability of the ic supply system. 6.2 disable function the inv pin doubles its function as a not-latched ic disable: a voltage below 0.2v shuts down the ic and reduces its consumption at a lower value. to restart the ic, the voltage on the pin must exceed 0.45 v. the main usage of this function is a remote on/off control input that can be driven by a pwm controller for power management purposes. however it also offers a certain degree of a dditional safety since it will ca use the ic to shutdown in case the lower resistor of the output divider is shorte d to ground or if the upper resistor is missing or fails open. 6.3 thd optimizer circuit the device is equipped with a special circ uit that reduces the conduction dead-angle occurring to the ac input curr ent near the zero-crossings of the line voltage (crossover distortion). in this way the thd (total harmon ic distortion) of the current is considerably reduced. a major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very lo w. this effect is magnified by the high- frequency filter capacitor placed after the br idge rectifier, which re tains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop.
L6562A application information 11/20 figure 3. thd optimization: standard tm pfc controller (left side) and L6562A (right side) to overcome this issue the circuit embedded in the device forces the pfc pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. this will resu lt in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequen cy filter capacitor after the bridge. the effect of the circuit is shown in figu re 2, where the key waveforms of a standard tm pfc controller are compared to those of the L6562A. essentially, the circuit artificially increases th e on-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. this offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. to maximally benefit from the thd optimizer circ uit, the high-frequency filter capacitor after the bridge rectifier should be minimized, co mpatibly with emi filtering needs. a large capacitance, in fact, introduces a conduction dea d-angle of the ac input current in itself - even with an ideal energy transfer by the pfc pre-regulator - thus making the action of the optimizer circuit little effective. imains vdrain imains vdrain input current input current mosfet's drain voltage mosfet's drain voltage rectified mains voltage rectified mains voltage input current input current
application information L6562A 12/20 6.4 operating with no auxiliar y winding on the boost inductor to generate the synchronization signal on the zcd pin, the typical approach requires the connection between the pin and an auxiliary winding of the boos t inductor through a limiting resistor. when the device is supplied by the ca scaded dc-dc converter, it is necessary to introduce a supplementary winding to t he pfc choke just to operate the zcd pin. another solution could be implemented by simply connecting the zcd pin to the drain of the power mosfet through an r-c network as shown in figure 3: in this way the high- frequency edges expe rienced by the drain will be transf erred to the zcd pin, hence arming and triggering the zcd comparator. also in this case the resistance value must be properly chosen to limit the current sourced/sunk by the zcd pin. recommended values for these components are 22pf (or 33pf) for c zcd and 330k for r zcd . with these values proper operation is guaranteed even with few volts difference between the regula ted output voltage and the peak input voltage figure 4. zcd pin synchroniza tion without auxiliary winding L6562A c zcd r zcd 5 zcd
L6562A application information 13/20 6.5 comparison between the L6562A and the l6562 the L6562A is not a direct drop-in replacement of the l6562, even if both have the same pin-out. one function (disable) has been relocated. table 2 compares the two devices, i.e. those pa rameters that may result in different values of the external components. the parameters th at have the most signi ficant impact on the design, i.e. that definitely require external component changes when converting an l6562- based design to the L6562A, are highlighted in bold. the lower value (-36%) for the clamp level of t he current sense reference voltage allows the use of a lower sense resistor for the same peak current, with a proportional reduction of the associated power dissipation. essentially, the advantage is the reduction of the power dissipated in a single point (hotspot), which is a considerable benefit in applications where heat removal is critical as in adapters closed/plastic case. the lower value for the dynamic ovp triggering current allows the use of a higher resistance value (+48%) for the upper resistor of the divider sensing the output vo ltage of the pfc stage (keeping the same overvoltage level) with no significant increase of noise sensitivity. this reduction goes in favor of stand-by consumption in applicatio ns required to comply with energy saving regulations. table 5. L6562A vs. l6562 parameter l6562 L6562A ic turn-on & turn-off thresholds (typ.) 12/9.5 v 12.5/10 v turn-off threshold spread (max.) 0.8 v 0.5 v ic consumption before start-up (max.) 70 ua 60 ua multiplier gain (typ.) 0.6 0.38 current sense reference clamp (typ.) 1.7 v 1.08 v current sense propagation delay (delay-to-output) (typ.) 200 ns 175 ns dynamic ovp triggering current (typ.) 40 ua 27 ua zcd arm/trigger/clamp thresholds (typ.) 2.1/1.4/0. 7 v 1.4/0.7/0 v enable threshold (typ.) 0.3 v (1) 1. function located on pin 5 (zcd) 0.45 v (2) 2. function located on pin 1 (inv) gate-driver internal drop (max.) 2.6 v 2.2 v leading-edge blanking on current sense no yes
application examples and ideas L6562A 14/20 7 application examples and ideas figure 5. typical application ci rcuit (80w, wide-range mains) figure 6. typical application circuit (400 w, wide-range mains, fot-controlled) ntc 2.5 w 8 3 bridge df06m r1 1 mw c1 0.47 f 400v r3 15 kw c3 22 f 25v fuse 4a/250v r4 270 kw d1 1n4150 d2 1n5248b r7 100 w c5 12 nf r6 47 kw t 5 6 L6562A 7 21 r9 33 w mos1 stp8nm50 4 r11 750 kw c8 47 f 450v vo=400v po=80w r10a 0.68w 0.25w r13b 20 kw + - c4 100 nf c2 10nf d3 stth1l06 r8 22 k w c6 3300 nf r2 1 mw r5 270 kw r10b 0.68w 0.25w r12 750 kw c7 220 nf boost inductor spec (itacoil e2543/e) e25x13x7 core,n67 ferrite 1.5 mm gap for 0.7 mh primary inductance primary: 105 turns 20x0.1 mm secondary: 8 turns 0.1 mm r13a 18 kw vac 88v to 264v 8 3 b1 kbu8m r1a 1 m w c1 1 f 400v c3 1 f fuse 8a/250v r6 3.3 kw 56 L6562A 7 21 m1a stp12nm50 4 c10 330 f 450 v vout = 400v pout = 400w vac 88v to 264v r10a,b,c,d 0.39 w 1 w + - c2 10nf d2 stth8r06 r7 6.8 w c5 1 f r1b 1 m w r2 15 kw d3 1n4148 d5 1n4148 r4 15 kw c7 220 pf c6 100 pf ntc1 2.5 w d1 1n5406 c9 470 nf 630 v r5 47 kw r8 6.8 w d4 1n4148 m1b stp12nm50 r3 1.5 kw tr1 bc857 l1 r12b 20 kw c8 330 pf r9 330 w r11a 750 kw r12a 18 kw r11b 750 kw vcc 10.5 to 22 v l1: core pq40-30,pc44 material 1 mm air gap on centre leg, for 0.5 mh inductance 65 t of 32 x awg32 ( ? 0.2 mm) c4 100 nf
L6562A package mechanical data 15/20 8 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. th e maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com
package mechanical data L6562A 16/20 figure 7. package dimensions table 6. dip-8 mechanical data dim. mm inch min typ max min typ max a 3.32 0.131 a1 0.51 0.020 b 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 d 10.92 0.430 e 7.95 9.75 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 f 6.6 0.260 i 5.08 0.200 l 3.18 3.81 0.125 0.150 z 1.52 0.060
L6562A package mechanical data 17/20 note: d and f does not include mold flash or protrusions. mold flash or potrusions shall not exceed 0.15mm (.006inch) per side. figure 8. package dimensions table 7. so-8 mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.10 0.043 a1 0.050 0.150 0.002 0.006 a2 0.750 0.850 0.950 0.03 0.033 0.037 b 0.250 0.400 0.010 0.016 c 0.130 0.230 0.005 0.009 d (1) 2.900 3.000 3.100 0.114 0.118 0.122 e 4.650 4.900 5.150 0.183 0.193 0.20 e1 (1) 2.900 3.000 3.100 0.114 0.118 0.122 e 0.650 0.026 l 0.400 0.550 0.700 0.016 0.022 0.028 l1 0.950 0.037 k 0 (min.) 6 (max.) aaa 0.100 0.004
order codes L6562A 18/20 9 order codes table 8. order codes part number package packaging L6562An dip-8 tube L6562Ad so-8 tube L6562Adtr so-8 tape & reel
L6562A revision history 19/20 10 revision history table 9. revision history date revision changes 3-mar-2007 1 first release
L6562A 20/20 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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